`timescale 1ns / 1ps

// Mul
// P = A*B
// 34bit = 22bit * 12bit
module MUL22x12 (
input clk,
input 		[21:0] A,
input 		[11:0] B,
output 		[33:0] P
);


//************************ ASIC - begin **********************//
// P = A*B
// 34bit = 22bit * 12bit

reg [33 : 0] P_reg;

always @(posedge clk) begin
	P_reg <= A * B;		
end

assign P = P_reg;
//************************ ASIC - end   **********************//

endmodule
